1. Field of the Invention
The present invention relates to circuit design and, more particularly, to optimizing portions of a circuit design for a target device.
2. Description of the Related Art
Synthesis refers to the process of translating an abstract representation of a circuit design into a physical implementation of that circuit design on some variety of electronic device, such as a programmable logic device (PLD). The abstract representation of the circuit design usually is specified in programmatic form using a Hardware Description Language (HDL). On a more detailed level, synthesis of a circuit design refers to both logic synthesis and physical synthesis.
In general, logic synthesis refers to the translation of a Register Transfer Level (RTL) representation of a circuit design written in HDL into a gate-level representation of the circuit design. The gate-level representation is often specified as a netlist of logic primitives. Logic synthesis is performed purely according to the circuit design and the logical structure of the target device. No regard is accorded to the physical implementation, in reference to the placement of the circuit design. Thus, no wire delays, or estimates of wire delays, are used when determining the operational speed of the circuit design during logic synthesis.
By comparison, physical synthesis refers, in general, to re-synthesizing the gate-level representation of the circuit design. This re-synthesis accounts for delays (or estimates of delays) of wires used to interconnect the various blocks of the circuit design on the target device. At this point, timing criticality of various portions of the circuit design on the target device can be evaluated. Re-synthesis undertaken during physical synthesis is an effective way of optimizing the circuit design since the process occurs closer to the actual physical implementation phase and, thus, more accurately models circuit behavior when determining whether design goals have been, or will be, met.
During physical synthesis, the components of the circuit design are assigned to specific locations on the target device and then routed. The process of assigning components to specific sites of the target device is referred to as “placement”. Typically, components of the circuit design are placed by attempting to optimize objectives including, but not limited to, total wire length of the physical implementation, the timing characteristics of the physical implementation, congestion, power consumption, and the like. As the circuit design has not yet been routed, quantities involving timing and wire length are computed using various estimating techniques.
In any case, the optimization of these objectives usually is performed on a global level with respect to the entire circuit design. With a view on global optimization, however, it often is the case that one or more regions of the circuit design are implemented in a less than optimal fashion. One example of this situation pertains to wire length and timing. Optimizing the global wire length of a circuit design tends to conserve limited routing resources. If wire length is valued too highly, one or more regions of the circuit design may suffer in terms of timing. That is, in an effort to reduce the total wire length of the circuit design, one or more regions of the circuit design may not meet established timing requirements. Once the circuit design is placed, it can be routed.
In such situations, it may be necessary to modify the circuit design to ensure that the resulting physical implementation meets all established objectives, including timing. Conventional techniques for dealing with this problem have involved multiple iterations between re-synthesis and place and route tools until the results are satisfactory. This iterative process, however, can be very time consuming, particularly since the entire circuit design, comprising upwards of thousands of netlist regions, is optimized during physical synthesis.
It would be beneficial to implement changes in a circuit design in a manner which overcomes the limitations described above.